Thesis BELLE2-PTHESIS-2016-005

Development of FPGA-Based Algorithms for the Data Acquisition of the Belle II Pixel Detector

Thomas Geßler ; Sören Lange, ; Wolfgang Kühn

II. Physikalisches Institut Giessen

Abstract: The pixel detector and Belle II data-acquisition systems impose various re- quirements on the performance of the ONSEN system, including a data through- put of almost 600 MB/s and a memory bandwidth of about 1 GB/s for every of the 32 modules performing the data reduction. The ONSEN system uses high-speed serial I/O links and low-level memory-controller interfaces to achieve these values. Small-scale tests show that the performance of the implemented logic surpasses the requirements, with a maintained input data rate of 621.6 MB/s and a memory bandwidth of up to 1683 MB/s. During tests of a pixel-detector module at the DESY test-beam facility, including the scaled-down Belle II data- acquisition system, more than 20 million events were recorded with the ONSEN system.

Note: Presented on 12 10 2015
Note: PhD

The record appears in these collections:
Books, Theses & Reports > Theses > PhD Theses

 Record created 2016-10-13, last modified 2016-10-13

Download fulltext

Rate this document:

Rate this document:
(Not yet reviewed)