000000416 001__ 416
000000416 005__ 20161013123553.0
000000416 037__ $$aBELLE2-PTHESIS-2016-005
000000416 041__ $$aeng
000000416 100__ $$aThomas Geßler
000000416 245__ $$aDevelopment of FPGA-Based Algorithms for the Data Acquisition of the Belle II Pixel Detector
000000416 260__ $$aGiessen$$bII. Physikalisches Institut$$c2015
000000416 300__ $$a230
000000416 500__ $$aPresented on 12 10 2015
000000416 502__ $$aPhD$$bGiessen, University Giessen$$c2015
000000416 520__ $$aThe pixel detector and Belle II data-acquisition systems impose various re- quirements on the performance of the ONSEN system, including a data through- put of almost 600 MB/s and a memory bandwidth of about 1 GB/s for every of the 32 modules performing the data reduction. The ONSEN system uses high-speed serial I/O links and low-level memory-controller interfaces to achieve these values. Small-scale tests show that the performance of the implemented logic surpasses the requirements, with a maintained input data rate of 621.6 MB/s and a memory bandwidth of up to 1683 MB/s. During tests of a pixel-detector module at the DESY test-beam facility, including the scaled-down Belle II data- acquisition system, more than 20 million events were recorded with the ONSEN system.
000000416 700__ $$aSören Lange, $$edir.
000000416 700__ $$aWolfgang Kühn$$edir.
000000416 8560_ $$fjens.soeren.lange@desy.de
000000416 8564_ $$uhttps://docs.belle2.org/record/416/files/BELLE2-PTHESIS-2016-005.pdf
000000416 980__ $$aTHESIS