Anna Tikhonova ; Alexander Kuzmin

2022
Novosibirsk State University Novosibirsk

Abstract: Since 2018, KEK research organisation (Tsukuba, Japan) is conducting experiments with Belle II detector at $e^+e^-$ collider SuperKEKB. Since Belle II experiment aims to study the CP violation parameters in rare decays of B- and D-mesons, SuperKEKB collider has been upgraded to increase its luminosity. The design luminosity of SuperKEKB collider is $6\cdot10^{35}$ cm$^{-2}$ s$^{-1}$, which is higher than previously achieved world record at KEKB by a factor of 30. One of the main Belle II detector subsystems is an electromagnetic calorimeter (ECL), with its main purpose being the registration of photons with high efficiency and determination of photons energy and coordinates. The ECL consists of 8736 CsI(Tl) counters. Scintillation light from CsI(Tl) crystals is registered by photodiodes, shaped, digitized and fitted. Shape fit reconstructs amplitude and time of the signal. Besides that, ECL can be used to separate hadrons from photons and electrons by signal shape, which depends on the density of the ionisation losses dE/dx. Currently, the contribution of hadron component is determined in the offline processing with a TMinuit class of ROOT library. In order to do this, ECL electronics saves waveform data for signals with the amplitude higher than 50 MeV. However, it would be difficult to continue saving all of high-amplitude waveforms with the increased trigger rate at the design luminosity. Thus it is necessary to implement shape fit with hadron component in the ECL electronics. This work aims to develop an algorithm that simulates the reconstruction of electron-photon and hadron components in the ECL readout electronics, focusing on the following tasks: 1. Simulation of the output signal from CsI(Tl) counters. 2. Development of the standalone shape fitting algorithm with hadron component. 3. Study of the algorithm accuracy. 4. Comparsion of the implemented algorithm with the offline fit implementation. 5. Preparation for the implementation in FPGA. 6. Study of possible upgrades of the ECL readout electronics.

Note: Presented on 21 06 2022
Note: MSc