Development and Testing of Depleted Monolithic Active Pixel Sensors in 180 nm CMOS technology for the Belle II VTX Upgrade

Sumitted to PubDB: 2026-10-27

Category: Phd Thesis

Tags: Upgrade

Principal Authors Maximilian Babeluk, Christoph Schwanda
Date 2026-08-01
Belle II Number BELLE2-PTHESIS-2026-027
Abstract Depleted Monolithic Active PixelSensors (DMAPS) have been the subject of increasing interest in detector research for particle physics in recent years.New high-resistivity, mixed-signal silicon manufacturing processes enable pixel sensors with not only analog signal amplification but powerful digital data processing.This is a major simplification compared tothe conventional hybrid sensor approach. With DMAPS, a single piece of silicon is the active sensing element, and only a few data- and power connections per chip to the data acquisition system are required. The Belle II experiment is located at the SuperKEKB collider in Japan.Electrons and positrons collide with a center of mass energy of 10.58 GeV at extreme luminosity. A key objective is high-precision measurement of the standard model with a special focus on the B-sector. To allow the desired precision, a minimal material budget is required for the detector to reduce multiple scattering as much as possible.Therefore, DMAPS are a perfect candidate for upgrading the Belle II vertex detector. The Optimized BeLle Ii piXel sensor (OBELIX) is a DMAPS chip currently under development, intended for the upgrade of the Belle II Vertex detector scheduled for 2032. The OBELIX chip is based on the TJ-Monopix2 small-electrode DMAPS chip and uses a modification of the Tower180 nm imaging CMOS technology. While the pixel matrix of OBELIX is inherited from TJ-Monopix2 with only small adaptations, the periphery is thoroughly reworked. The OBELIX chip contains voltage regulators and a monitoring system with multiple temperature sensors and taps to measure voltage drop on chip. On the digital side of the periphery, the complete data processing is newly implemented. This includes a trigger memory to match the requirements for Belle II. In addition, a precision timing module allows for increased time resolution. The chip is also capable of sending low-granularity hit-data to the first-level trigger system of Belle II in parallel to normal operation. This thesis focuses on the development of the digital periphery of the OBELIX chip while also giving insight into the whole upgrade project and the other features of the OBELIX chip. The design is explained in technical detail, and simulations are conducted for performance evaluation at nominal- and overload conditions. In particular, the author has implemented all of the new features of the digital periphery. This includes the trigger memory with performance simulations using realistic data patterns. Furthermore, the author conceptualized and implemented the precision timing module as well as the module for contribution to the Belle II first level trigger. The performance of the TJ-Monopix2 chip has been evaluated using laboratory measurements and test-beams by the author. The timing measurements and analyses have been performed by the author, and significant contributions have been made to the efficiency measurements at the test-beams.
Institute MBI Vienna

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