Development of FPGA-Based Algorithms for the Data Acquisition of the Belle II Pixel Detector

Sumitted to PubDB: 2016-10-13

Category: Phd Thesis, Visibility: Public

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Authors	Thomas Geßler, Wolfgang Kuehn
Non-Belle II authors	Sören Lange
Date	Jan. 1, 2015
Belle II Number	BELLE2-PTHESIS-2016-005
Abstract	The pixel detector and Belle II data-acquisition systems impose various re- quirements on the performance of the ONSEN system, including a data through- put of almost 600 MB/s and a memory bandwidth of about 1 GB/s for every of the 32 modules performing the data reduction. The ONSEN system uses high-speed serial I/O links and low-level memory-controller interfaces to achieve these values. Small-scale tests show that the performance of the implemented logic surpasses the requirements, with a maintained input data rate of 621.6 MB/s and a memory bandwidth of up to 1683 MB/s. During tests of a pixel-detector module at the DESY test-beam facility, including the scaled-down Belle II data- acquisition system, more than 20 million events were recorded with the ONSEN system.
Conference	Giessen